1. Field
The invention relates to providing direct-current (DC) isolation for electrical signals.
2. Background Information
As is well-known, a series capacitor, as illustrated in FIG. 2, may be employed to block direct current (DC) voltage levels on a DC balanced signal. In this context, the term "DC balanced" refers to the time average of the signal converging to a DC, fixed signal level that is independent of the data signal values, typically zero volts for differential signaling. This is illustrated in FIG. 2 in which a capacitor 230 is coupled in series with an operational amplifier 210. For the embodiment illustrated in FIG. 2, V.sub.bias provides the center point for the signal V.sub.int.
FIG. 3 illustrates the corresponding signals along a time axis. The biasing scheme operates satisfactorily so long as the signal has an average value independent of data signals. In a system employing binary digital signals, this means a balanced number of "ones" and "zeros." However, in many systems, this balancing of ones and zeros is not assured. For example, although the invention is not limited in scope in this respect, the 1394A protocol specification, Draft 2.0, dated Mar. 15, 1998, available from the Institute of Electrical and Electronic Engineers (IEEE), (hereinafter, "1394A"), does not ensure a balanced number of ones and zeros. Therefore, a long run of zeros may cause the internal node, such as V.sub.int in FIG. 2, to drift up to the bias level instead of remaining at the level indicating a "zero." This effect may be more pronounced in multi-level systems, where multiple voltage signal levels are sensed. For example, the 1394A specification employs three logic levels, zero, "z," and one. Therefore, if a long string of zeros were sent, V.sub.int would drift up and result in a z being mistakenly interpreted, as illustrated in FIG. 3, for example. A need, therefore, exists to address this shortcoming in such unbalanced systems.